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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20878-3E
FLASH MEMORY
CMOS
64M (8M x 8) BIT NAND-type
MBM30LV0064
s DESCRIPTION
The MBM30LV0064 device is a single 3.3 V 8M x 8 bit NAND flash memory organized as 528 byte x 16 pages x 1024 blocks. Each 528 byte page contains 16 bytes of optionally selected spare area which may be used to store ECC code(Specifications indecated are on condition that ECC system would be combined.). Program and read data is transferred between the memory array and page register in 528 byte increments. A 528 byte page can be programmed in 200 s and an 8K byte block can be erased in 2 ms under typical conditions. An internal controller automates all program and erase operations including the verification of data margins. Data within a page can be read with a 50 ns cycle time per byte. The I/O pins are utilized for both address and data input/ output as well as command inputs. The MBM30LV0064 is an ideal solution for applications requiring mass nonvolatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other uses which require high density and non-volatile storage.
s PRODUCT LINE UP
Part No. Operating Temperature VCC Read Power Dissipation (Max.) Erase / Program TTL Standby CMOS Standby MBM30LV0064 -40C to +85C +2.7 V to +3.6 V 72 mW 72 mW 3.6 mW 0.18 mW
s PACKAGES
44-pin plastic TSOP (II)
Marking Side
Marking Side
(FPT-44P-M07) (Normal Bend)
(FPT-44P-M08) (Reverse Bend)
MBM30LV0064
s FEATURES
* 3.3 V-only operating voltage (2.7 V to 3.6 V) Minimizes system level power requirements * Organization Memory Cell Array : (8M + 256K) x8 bit Data Register : (512 + 16) x8 bit * Automatic Program and Erase Page Program : (512 + 16) Byte Block Erase : (8K + 256) Byte * 528 Byte Page Read Operation Random Access : 7 s (Max.) Serial Access : 35 ns (Max.) * Fast Program and Erase Program Time : 200 s (Typ.) / page Block Erase Time : 2 ms (Typ.) / block * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection * 1,000,000 write/erase cycle guaranteed (ECC system required) * Command Register Operation * Package 44(40)-pin TSOP Type II (0.8 mm pitch) Normal/Reverse Type * Data Retention: 10 years
2
MBM30LV0064
s PIN ASSIGNMENTS
TOP VIEW Vss CLE ALE WE WP N.C. N.C. N.C. N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 N.C. N.C. N.C. N.C. N.C. I/O0 I/O1 I/O2 I/O3 Vss 13 14 15 16 17 18 19 20 21 22 FPT-44P-M07 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 N.C. N.C. N.C. N.C. N.C. I/O7 I/O6 I/O5 I/O4 Vccq N.C. N.C. N.C. N.C. N.C. I/O7 I/O6 I/O5 I/O4 Vccq Vcc CE RE R/B SE N.C. N.C. N.C. N.C. N.C. Vcc CE RE R/B SE N.C. N.C. N.C. N.C. N.C. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 FPT-44P-M08 TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 N.C. N.C. N.C. N.C. N.C. I/O0 I/O1 I/O2 I/O3 Vss Vss CLE ALE WE WP N.C. N.C. N.C. N.C. N.C.
3
MBM30LV0064
s PIN DESCRIPTIONS
Pin Number Pin Name 18 to 21 24 to 27 I/O0 to I/O7 Descriptions Data Input/Output The I/O ports are used for transferring command, address, and input/output data into and out of the device. The I/O pins will be high impedance when the outputs are disabled or the device is not selected. Command Latch Enable The CLE signal enables the acquisition of the made command into the internal command register. When CLE="H", command are latched into the command register from the I/O port upon the rising edge of the WE signal. Address Latch Enable The ALE signal enables the acquisition of either address or data into the internal address/data register. The rising edge of WE latch in addresses when ALE is high and data when ALE is low. Chip Enable The CE signal is used to select the device. When CE is high, the device enters a low power standby mode. If CE transitions high during a read operation, the standby mode will be entered. However, the CE signal is ignored if the device is in a busy state(R/B=L) during a program or erase operation. Read Enable The RE signal controls the serial data output. The falling edge of RE drives the data onto the I/O bus and increments the column address counter by one. Write Enable The WE signal controls writes from the I/O port. Data, address, and commands on the I/O port are latched upon the rising of the WE pulse. Write Protect The WP signal protects the device against accidental erasure or programming during power up/down by disabling the internal high voltage generators. WP should be kept low when the device powers up until VCC is above 2.5 V. During power down, WP should be low when VCC falls below 2.5 V. Spare Area Enable The SE input enables the spare area during sequential data input, page program, and Read 1. Ready Busy Output The R/B output signal is used to indicate the operating status of the device. During program, erase, or read, R/B is low and will return high upon the completion of the operation. The output buffer for this signal is an open drain. Output Buffer Power Supply The VCCq input supplies the power to the I/O interface logic. This power line is electrically isolated from VCC for the purpose of supporting 5V tolerant I/O. Power Supply Ground No Connection
2
CLE
3
ALE
43
CE
42
RE
4
WE
5
WP
40
SE
41
R/B
23 44 1,22 6 to 17 28 to 39
VCCq VCC VSS N.C.
4
MBM30LV0064
s BLOCK DIAGRAM
R/B High Voltage Pumps ALE CLE SE WP CE RE WE Y-Decoder Data Register & S/A State Machine X Decoder Command Register Memory Array
Data Register & S/A Y-Decoder
Address Register
Status Register I/O Register & Buffer VCC VCCq VSS I/O0 to I/O7
5
MBM30LV0064
s SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT
The Program operation is implemented in page units while the Erase operation is carried out in block units.
I/O0 Register 512 16 I/O7
Read and Program operation are executed through Register Register = 1 page size
16 pages 1 block 16384 pages (1024 blocks)
Memory Cell Array
8 I/O
528
1) A page consists of (512+16) bytes; - 512 bytes for main memory - 16 bytes for redundancy or other use 2) A block consists of 16 pages; (8K+256) bytes. 3) Total device density = 528 bytes x 16 pages x 1024 blocks.
Figure 1
Schematic Cell Layout
Table 1 I/O0 First Cycle Second Cycle Third Cycle A0 A9 A17 I/O1 A1 A10 A18 I/O2 A2 A11 A19
Addressing I/O3 A3 A12 A20 I/O4 A4 A13 A21 I/O5 A5 A14 A22 I/O6 A6 A15 X* I/O7 A7 A16 X*
A0 to A7 : column address A9 to A22 : page address A13 to A22 : block address A9 to A12 : Page address in block (A8 is automatically set to "Low" or "High" by the "00h" command or the "01h" command in device inside.) * : X = VIH or VIL
6
MBM30LV0064
s DEVICE BUS OPERATIONS
Table 2 Mode Read Mode Command Input Address Input (3 clock) CLE H L L L H L L X X X X Operation Table *1 ALE L H L L L H L X X X X CE L L L L L L L X X X H X X X X H H H H H X X X X WE RE H H H SE X *4 X *4 L/H *3 L/H *3 X *4 X *4 L/H *3 L/H *3 X X WP X X X X H H H H H L
During Read (Busy) Sequential Read & Data Output Program/ Command Input Erase Address Input (2 or 3 clock) Mode Data Input During Program (Busy) During Erase (Busy) Write Protect Stand-by *1: H: VIH, L: VIL, X: VIH or VIL
0 V/VCC*2 0 V/VCC*2
*2: WP should be biased to CMOS high or CMOS low for standby. *3: When SE is high, spare area is deselected. *4: If 50h command is input and read/program operation is executed only for spare area, SE must be low at the command/address input. Table 3 Operation Output Select Output Deselect Standby *: H: VIH, L: VIL, X: VIH or VIL CLE L L X ALE L L X Read Mode Operation Status * CE L L H WE H H X RE L H X I/O0 to I/O7 Data Output High Impedance High Impedance Power Supply Active Active Standby
7
MBM30LV0064
s COMMAND OPERATION
Table 4 Function Read (1) Read (2) Read (3) Sequential Data Input Page Program Block Erase Reset Status Read ID Read 1st Cycle 00h *1 01h *2 50h *3 80h 10h 60h FFh 70h 90h Command Table 2nd Cycle -- -- -- -- -- D0h -- -- -- Acceptable Command During Busy State
*1: The 00h Command defines starting Address on the 1st half Page. *2: The 01h Command defines starting Address on the 2nd half Page. *3: The 50h Command is valid only When SE is low level.
8
MBM30LV0064
s FUNCTIONAL DESCRIPTION
READ MODE
There are three distinct commands used for the read operation: 00h, 01h, and 50h. After the command cycle, three address cycles are used to input the starting address. Upon the rising edge of the final WE pulse, there is a 7 s latency in which the 528 byte page is transferred to the data register. The R/B signal may be used to monitor the completion of the data transfer. In the read operation, the CE signal must stay "Low" after the third address input and during Busy state. If the CE signal goes High during this period, the read operation will be terminated and then the standby mode will be entered. Once the page of data has been loaded into the data register, it may be clocked out with consecutive 50 ns RE pulses. Each RE pulse will automatically advance the column address by one. Once the last column has been read, the page address will automatically increment by one and the data register will be updated with the new page after 7 s. The 00h Read command will set the pointer to the first half page of the array while the 01h Read command will set it in the second half. It may be logical to think of 00h as a command which sets A8 = 0 while 01h sets A8 = 1. The 50h command set the pointer to the spare area, consisting of columns 512 to 527. During this read mode, A3 to A0 is used to set the starting address of the spare area. As with the 00h and 01h operations, once the spare area page is loaded into the data register, it may be read out by RE pulses. Each RE pulse will increment the column address until the final column (527) is reached. At this time, the pointer will be reset to column 512 while the page address is incriminated and the data register is updated. The 00h or 01h command is required to move the pointer back into the main array area.
Read (1), (2): 00h/01h
The Read (1), (2) mode is invoked by latching the 00h or 01h command into the command register. This mode (00h) will be automatically selected when the device powers up.
CE
CLE ALE WE RE R/B I/O0 to I/O7 Command 01h 00h 0 Page (Row) X Address 255 511 527
Starting Address Y X X
Data Output
Y Y (Column Address)
Figure 2
Read Mode (1), (2) Operation 9
MBM30LV0064
Read (3): 50h
The Read (3) mode has identical timing to that of Read (1) and (2). However, while Read (1) and (2) are used to access the array, Read (3) is used to access the 16 byte spare area. When the 50h command is executed, the pointer will be set to an address space between columns 512 and 527. The values of Y will complete the address decoding. During this operation, only address bits A3 to A0 are used to determine the starting column address; A7 to A4 are ignored. A22 to A9 are used to determine the starting row address.
CE CLE ALE WE RE R/B I/O0 to I/O7 Starting Address Y X X Command 50h 0 Page (Row) X Address 255 511 527 Data Output
Y (Column Address)
Figure 3
Read Mode (3) Operation
Sequential Read
Each RE pulse used to output data from the data register will cause the column address pointer to increment by one. When the final column has been reached, the next page will be automatically loaded into the data register. The R/B signal may be used to monitor the completion of the data transfer.
R/B I/O0 to I/O7 00h/01h/50h 0 255 Address Input 255 Data 511 527 0 Data 255 511 527 0 Data 255 511 527
511 527 0
00h, SE=L
01h, SE=L
00h, SE=H
50h, SE=L
Figure 4
Sequential Read
10
MBM30LV0064
Page Program: 80h, 10h
The device is programmed either by the page or partial page. Programming is done by issuing the 80h command followed by three address cycles then serial data input. The 80h command may be preceded by either 00h, 01h or 50h to set the pointer to either the first half page, second half page, or spare area respectively. If the pointer command is not specifically issued, its location is determined by its previous use (see Application Note (2) ). After the serial data input, any column address which did not receive new data will not be programmed. This enables a page to be partially programmed. After the data has been entered, the 10h command will initiate the embedded programming process. If the 10h command is issued without loading any new data, programming will not be initiated. A given page may not be partially programmed more than ten consecutive times without an intervening erase operation. During the programming cycle, the R/B pin or Status Register bit I/O6 may be used to monitor the completion of the programming cycle. Only the Reset and Read Status commands are valid while programming is in progress. After programming, the Status Register bit I/O0 should be checked to verify whether the procedure was successful or not.
R/B
I/O0 to I/O7
80h
Address and Data Input
10h
70h
I/O0 0 = Pass 1 = Fail
Figure 5
Page Program
Block Erase: 60h
The device data is erased in a block consisting of sixteen pages. The erase operation begins with the 60h command followed by two address cycles in which the block to be erased is entered. While the two address cycles require A22 to A9 to be entered, A12 to A9 are don't care bits. Once the block address is successfully loaded, the D0h command is entered to initiate the erase operation. The R/B signal may be used to monitor the completion of the cycle. Upon completion, the Status Register bit I/O0 should be used to verify a successful erase.
R/B
I/O0 to I/O7
60h
Address Input
D0h
70h
I/O0 0 = Pass 1 = Fail
Figure 6
Block Erase
11
MBM30LV0064
Read ID: 90h
This mode allows the identification of the manufacturer and product. After the 90h command cycle, one address cycle follows in which 00h is entered. The next two RE pulses will output the manufacturer and device code respectively.
RE
I/O0 to I/O7
90h
00h
04h Manufacturer Code
E6h Device Code
Figure 7
Read ID Operation
Table 5 I/O7 Manufacturer Device 0 1 I/O6 0 1 I/O5 0 1
Code Table I/O4 0 0 I/O3 0 0 I/O2 1 1 I/O 1 0 1 I/O0 0 0 Code 04h E6h
Status Read: 70h
The Status Register may be used to determine if the device is ready, in the write protect mode, or passed program/erase operations. After the 70h command is entered, the more recent falling edge of either CE or RE will output the contents of the status register to I/O0 to 7. The status register is continually updated and does not require either CE or RE to be toggled. By utilizing the CE pin, multiple devices with R/B pins wired together may be polled to determine their specific status. Table 6 Status I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Program/Erase Not Used Not Used Not Used Not Used Not Used Ready/Busy Write Protect 0 = Busy; 1 = Ready 0 = Protected; 1 = Unprotected Status Output Table Description 0 = Pass; 1 = Fail
12
MBM30LV0064
CE(1) ALE CLE WE RE
CE(2)
CE(N)
Device(1)
Device(2)
Device(N)
8 I/O0 to I/O7 R/B
R/B
ALE CLE WE CE(1) CE(N) RE I/O0 to I/O7 70h 0/1 Status of Device(1) 70h 0/1 Status of Device(N)
Figure 8
Status Read
Reset
When the device is busy during program, erase, or read, it can be reset by entering the command FFh. If WP = 1, the Status Register will be set to C0h. If a reset command is issued while the device is in the reset state, the command will be ignored. If the device is reset during the program or erase operations, the internal high voltages will be discharged before R/B goes high.
R/B I/O0 to I/O7 FFh
13
MBM30LV0064
s ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature with Power Applied Storage Temperature Voltage on a I/O pin with Respect to Ground * Voltage on a pin Except I/O with Respect to Ground * Power Supply Voltage Symbol TA Tstg VI/O VIN VCC VCCq Rating Min. -40 -55 -0.6 -0.6 -0.6 -0.6 Max. +85 +125 VCCq +0.5 VCC +0.5 +5.5 +6.0 Unit C C V V V
*: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may under shoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input pins is VCC + 0.5 V and on I/O pins are VCCq + 0.5 V. During voltage transitions, input pins may overshoot to VCC +2.0 V for periods of up to 20 ns and I/O pins may overshoot to VCCq + 2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltages Supply Voltages Voltages Ambient Temperature Symbol VCC VCCq * VSS TA -40 Value Min. +2.7 +2.7 0 +85 Max. +3.6 +5.5 Unit V V V C
*: VCCq = 5.0 V 10% can be guaranteed on VCC 3.0 V. Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
14
MBM30LV0064
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Sequential Read Current Command Address Input Current Data Input Current Program Current Erase Current Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B) Symbol ICC1 ICC3 ICC4 ICC6 ICC7 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL Conditions tCYCLE = 50 ns, CE = VIL, IOUT = 0 mA tCYCLE = 50 ns, CE = VIL -- -- -- CE = VIH, WP = SE = 0 V/VCC CE = VCC -0.2 V, WP = SE = 0 V/ VCC VIN = 0 to 3.6 V VOUT = 0 to 3.6 V I/O pins Except I/O pins -- IOH = -400 A IOL = 2.1 mA VOL = 0.4 V Value Min. -- -- -- -- -- -- -- -- -- 2.0 2.0 -0.3 2.4 -- 8 Typ. 10 10 10 10 10 -- 10 -- -- -- -- -- -- -- 10 Max. 20 20 20 20 20 1 50 10 10 VCCq +0.3 VCC +0.3 0.8 -- 0.4 -- Unit mA mA mA mA mA mA A A A V V V V V mA
15
MBM30LV0064
2. AC Characteristics (Note 1)
Parameter CLE Setup Time CLE Hold Time CE Setup Time CE Hold Time Write Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time WP High to WE Low Ready to RE Falling Edge Read Pulse Width Read Cycle Time RE Access Time (Serial Data Access) CE High Time for the Last Address in Serial Read Cycle (Note 3) RE Access Time (ID Read) RE High to Output High Impedance CE High to Output High Impedance RE High Hold Time Output High Impedance to RE Falling Edge RE Access Time (Status Read) CE Access Time (Status Read) WE High to RE Low ALE Low to RE Low (ID Read) CE Low to RE Low (ID Read) Data Transfer from Memory Cell Array to Register WE High to Busy Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tWW tRR tRP tRC tREA tCEH tREAID tRHZ tCHZ tREH tIR tRSTO tCSTO tWHR tAR1 tCR tR tWB Value Min. 0 10 0 10 25 0 10 20 10 50 15 100 20 30 50 -- 100 -- 15 -- 15 0 -- -- 60 100 100 -- -- Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 -- 35 30 20 -- -- 35 45 -- -- -- 7 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns
(Continued)
16
MBM30LV0064
(Continued)
Parameter ALE Low to RE Low (Read Cycle) RE Last Clock Rising Edge to Busy (in Sequential Read) CE High to Ready (in Case of Interception by CE in Read Mode) (Note 2) Device Resetting Time (Read/Program/Erase) Notes: 1. AC Test Conditions: Operating range Input level Input comparison level Output data comparison level Output load Load capacitance (CL) Transition time (tT) 50 pF 5 ns VCC = 2.7 to 3.6 V VCC = 3.0 to 3.6 V Symbol tAR2 tRB tCRY tRST Value Min. 50 -- -- -- Max. -- 100 50 + tr (R/B) 5/10/500 Unit ns ns ns s
2.4 V/0.4 V 1.5 V/1.5 V 1.5 V/1.5 V 1TTL 100 pF
2. The time to go from CE high to Ready depends on the pull-up resister of the R/B pin (see Application Notes (6)) toward the end of this document. 3. In case that toggling CE to high after access to the last address (address 527) in the resister in the read mode (1), (2), and (3), the CE high time must be held for 100 ns or more when the delay time of CE with respect to RE is 0 to 200 ns (see the figure below). When the CE delay time is within 30 ns, the device is kept in the Ready state and will output no Busy signal.
17
MBM30LV0064
tCEH 100 ns
* CE RE A 525 509 R/B 526 510 527 511 A : 0 to 30 ns Busy signal is not output. *: VIH or VIL
Busy
18
MBM30LV0064
s ERASE AND PROGRAMMING PERFORMANCE
Parameter Average Programming Time Number of Programming Cycles on Same Page Block Erasing Time Number of Program/Erase Cycles Symbol tPROG N tBERASE P/E Value Min. -- -- -- 1 x 106 Typ. 200 -- 2 -- Max. 1000 10 10 -- ms *2 Unit s *1 Remarks
*1: Refer to Application Note (10) toward the end of this document. *2: Refer to Application Note (13) toward the end of this document. This specification is on conditions that ECC system would be combined.
s VALID BLOCKS
The MBM30LV0064 occasionally contains unusable blocks. Refer to Application Note (12) toward the end of this document. Value Parameter Symbol Unit Min. Typ. Max. Valid Block Number NVB 1014 1020 1024 Block
s PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Symbol CIN COUT VIN = 0 VOUT = 0 Condition Value Typ. -- -- Max. 10 10 Unit pF pF
Notes: 1. Test conditions TA = 25C, f = 1.0 MHz 2. Sampled, not 100% tested.
19
MBM30LV0064
s TIMING DIAGRAMS
CLE tCLS tCS CE tWP WE tALS ALE tDS I/O0 to I/O7 tDH tALH tCLH tCH
: VIH or VIL
Figure 9
Command Input Cycle Timing Diagram
CLE tCS CE
tCLS tWC tWH tWP tWP tWC tWH tWP
WE tALS ALE tDS I/O0 to I/O7 tDH tDS tDH tDS tDH tALH
A0 to A7
A9 to A16
A17 to A22 : VIH or VIL
Figure 10
Address Input Cycle Timing Diagram
20
MBM30LV0064
tCLH CLE tCH CE tALS ALE tWP WE tDS I/O0 to I/O7 * : SE = GND input : to DIN 527 = VCC input : to DIN 511 tDH tDS tDH tDS DIN * : VIH or VIL tDH tWH tWP tWP tWC
DINN
DINN+1
Figure 11
Data Input Cycle Timing Diagram
21
MBM30LV0064
tRC CE tRP RE tREA tRHZ tREA tRHZ tREA tRHZ tREH tRP tRP tCHZ
I/O0 to I/O7 tRR
R/B
Figure 12
Serial Read Cycle Timing Diagram
tCLS CLE tCLS tCLH CE tCS
tWP WE
tCH
tCSTO tCHZ tWHR
RE tDS tDH I/O0 to I/O7 70h
tIR tRHZ tRSTO Status Output
R/B
: VIH or VIL
Figure 13
Status Read Cycle Timing Diagram
22
MBM30LV0064
CLE tCLS CE tCS WE ALE tWB tALH RE I/O0 to I/O7 tDS tDH 00h tDS tDH tDS tDH tDS tDH A17 to A22 tREA DOUT N DOUT N+1 DOUT N+2 ** DOUT tRB tRR tRC tALS tWC tR tALH tAR2 tCRY tCLH tCH tCEH
A0 to A9 to A7 A16 Column address N
R/B **:SE = GND input : DOUT 527 = VCC input : DOUT 511 : VIH or VIL
Note: The CE signal must stay "Low" after the third address input and during Busy state. Figure 14 Read Cycle (1) Timing Diagram
CLE CE
tCLS
tCLH tCH tWC tR tALS tALH tWB tALH tAR2 tCHZ
tCS WE ALE tDS tDH I/O0 to I/O7 00h
tRR
tRC tRHZ tREA DOUT DOUT N N+1 DOUT N+2
RE
tDS tDH
tDS tDH
tDS tDH A17 to A22
A0 to A9 to A7 A16 Column address N ***
R/B ***:Read Operation using 00h Command Read Operation using 01h Command N : 0 to 255 N : 256 to 511 : VIH or VIL
Note: The CE signal must stay "Low" after the third address input and during Busy state. Figure 15 Read Cycle (1) Timing Diagram: Interrupted by CE
23
MBM30LV0064
CLE
tCLS tCS
tCLH tCH
CE tR tALS tALH tALH RE tDS tDH I/O0 to I/O7 01h tDS tDH tRR A0 to A9 to A7 A16 Column address M A17 to A22 DOUT tREA DOUT ** DOUT tRC tWB
WE ALE
tAR2
256 + M 256 + M + 1
R/B **: SE = GND input : DOUT 527 = VCC input : DOUT 511 : VIH or VIL
Note: The CE signal must stay "Low" after the third address input and during Busy state. Figure 16 Read Cycle (2) Timing Diagram
CLE
tCLS tCS
tCLH tCH
CE tR tALS tALH tALH RE tDS tDH I/O0 to I/O7 50h tDS tDH tRR A0 to A9 to A7 A16 Column address M A17 to A22 DOUT tREA DOUT ** DOUT tRC tWB
WE ALE
tAR2
512 + M 512 + M + 1 527
R/B **: SE = GND input : DOUT 527 = Do not input VCC : VIH or VIL
Note: The CE signal must stay "Low" after the third address input and during Busy state. Figure 17 Read Cycle (3) Timing Diagram
24
MBM30LV0064
CLE CE
WE ALE RE I/O0 to I/O7 00h A0 to A9 to A17 to A7 A16 A22 Column Page Address Address N M R/B Page M Access **: SE = GND input : DOUT 527 = VCC input : DOUT 511 : VIH or VIL tR N N+1 N+2 ** tR 0 1 2 **
Note: The CE signal must stay "Low" after the third address input and during Busy state. Figure 18 Sequential Read (1) Timing Diagram
CLE CE
WE ALE RE I/O0 to I/O7 01h A0 to A9 to A17 to A7 A16 A22 Column Page Address Address N M R/B Page M Access **: SE = GND input : DOUT 527 = VCC input : DOUT 511 Page M + 1 Access : VIH or VIL tR 256 256 256 + + + N N+1N+2 ** tR 0 1 2 **
Note: The CE signal must stay "Low" after the third address input and during Busy state. Figure 19 Sequential Read (2) Timing Diagram 25
MBM30LV0064
CLE CE
WE ALE RE I/O0 to I/O7 50h A0 to A9 to A17 to A7 A16 A22 Column Page Address Address N M R/B Page M Access **: SE = GND input : DOUT 527 = Do not input VCC Page M + 1 Access : VIH or VIL tR 512 512 512 + + + N N+1N+2 ** tR 512 513 514 **
Note: The CE signal must stay "Low" after the third address input and during Busy state. Figure 20 Sequential Read Cycle (3) Timing Diagram
26
MBM30LV0064
CLE
tCLS tCLS tCLS tCS tCS tCH
CE WE
tALS tALH tALH
tALS tPROG tWB tDH tDS DIN
N
ALE
RE tDS I/O0 to I/O7 R/B
tDH 80h
tDS
tDH
A0 to A7 A9 to A16 A17 to A22
tDH DIN DIN *
Status Output
tDS
N+1
10h
70h
*: SE = GND input : to DIN 527 = VCC input : to DIN 511
: VIH or VIL
Figure 21
Auto Program Operation Timing Diagram
CLE
tCLS tCLH tCLS
CE tCS WE tALS ALE tALH tWB tBERASE
RE I/O0 to I/O7 R/B
tDS tDH 60h
A9 to A16 A17 to A22
D0h
70h
Status Output
Auto Block Erase Setup Command
Erase Start Command
Status Read Command : VIH or VIL
Figure 22
Auto Block Erase Timing Diagram
27
MBM30LV0064
CLE tCS CE
tCLS tCH tCLS
tCS WE tALH ALE RE I/O0 to I/O7 tDS tDH 90h tALS
tALH tCH tCR tAR1
00h tREAID Address Input
04h tREAID
E6h
Maker Code Device Code : VIH or VIL
Figure 23
ID Read Operation Timing Diagram
28
MBM30LV0064
s APPLICATION NOTES AND COMMENTS
(1) Prohibition of unspecified commands The operation commands are listed in Table 4. Data input as a command other than the specified commands in Table 4 is prohibited. Stored data may be corrupted if an unspecified command is entered during the command cycle. (2) Pointer Action for Program Operation The pointer action can be done for program operation as follows.
Start Yes
Only 50h area Program? No No Start address is in 00h area? Yes Input 01h Command
Input 50h Command *1
Input 00h Command *2
Program Sequence
*1: If read operation was done setting start address in 50h area in previous use, the 50h command input can be skipped. *2: If read operation was done at 00h or (and) 01h area in previous use, the 00h command input can be skipped. *3: The read command means 00h, 01h or 50h.
Continue to Program? Yes Start address area (00h,01h,50h) is the same as the previous? Yes 0 255 511 527 The pointer is 01h? No
No
No
Start address area is changed from 01h to 00h? No Input read command *3
Yes
Yes Set 01h command
00h
01h
50h Yes
Program Sequence
Continue to Program? No End
Figure 24
Pointer Action Flow Chart 29
MBM30LV0064
(3) Acceptable commands after serial input command `80h' When the serial input command (80h) is input for program execution, commands other than the program execution command (10h) or reset command (FFh) should not be input.
80 WE R/B Address input FF
Figure 25
Reset Command After 80h Input
If a command other than `10h' or `FFh' is input, the program operation is not performed.
80 XX Other command 10 Programming will not be executed. In case of this operation, the FFh command is needed.
(4) Status read during the read operation
00 00 CE WE R/B RE N address Status read command input Status read Status output 70 [A]
Figure 26
Status Read During Read Operation
When the status read command (70h) is input during reading, the next RE clock signal can be input to read the value of the internal status register. Since the internal operation mode is held in Status Read, read data will not be output even if the RE clock signal is input after becoming ready. Status Read is therefore disabled at reading. When the read command (00h) is input during the period [A], the internal operation mode of the device can be canceled, making it possible to read data at address N without inputting Add. (5) Auto program failure
80 10 70 I/O Fail 80 10
Address Data M input 80 10 M
Address Data N input If programming at page address (M) fails, data should be programmed at the page address (N) of another block. Data input at first programming at page address (M) is lost. So address input using the 80h command must follow the same procedure as data input.
N
Figure 27 30
Auto Program Failure
MBM30LV0064
(6) R/B: Termination of the Ready/Busy pin (R/B) The R/B is open-drain output. When using the R/B, R/B must be pulled up VCC by a resistor.
VCC VCC Device CL VSS R R/B
R= =
VCC (Max.) -- VOL IOL + IL 3.2 V 8 mA + IL
Figure 28
Termination for R/B
(7) Power On/Off Sequence: After power-off, each input signal level may be undefined. Use the WP signal as shown in the figure below.
2.7 V 2.5 V VCC 0V DON'T CARE CE, WE, RE CLE, ALE WP VIL VIH Operation VIL DON'T CARE
Figure 29
Power On/Off Sequence
31
MBM30LV0064
(8) Setup for WP Signal A Low-level WP signal will force erasing and programming to be reset. To control, use the WP signal as shown below.
Program WE DIN WP R/B tWW 100 ns (Min.) Program Prohibition WE DIN WP R/B tWW 100 ns (Min.) 80 10 80 10
Erase WE DIN WP R/B tWW 100 ns (Min.) 60 D0
Erase Prohibition WE DIN WP R/B tWW 100 ns (Min.) 60 D0
32
MBM30LV0064
(9) Address input in 4 cycles The device will get addresses in three cycles. If addresses are input in four cycles, address input in the fourth cycle will be ignored in the chip.
Read operation
CLE CE WE ALE
I/O0 to I/O7 00h, 01h or 50h R/B Internal read operation starts when WE in the third cycle goes high. Address input ignored
Figure 30
Read Operation when 4 Address Cycles are Input
Program operation
CLE CE WE ALE
I/O0 to I/O7
80h Address input ignored Data input
Figure 31
Program Operation when 4 Address Cycles are Input
33
MBM30LV0064
(10) Divided programming on same page The device uses the page programming method that allows programming up to ten times on the same page. The procedure for divided programming (programming on a part of one page) is shown below.
The first programming Column A Page N
Column B "No Input" or "1"
Data Pattern 1
The second programming Column C Page N The third programming Column E Page N Result Column A Page N Column B Column C `1' Column D Column E `1' Data Pattern 1 Data Pattern 2 Data Pattern 3 "No Input" or "1" Column F "No Input" or "1" Column F `1' Data Pattern 3 "No Input" or "1" Column D "No Input" or "1" Data Pattern 2
Figure 32
Divided Program in the Same Page
(11) Notification for RE Signal When the device is in the read mode, the RE signal causes the internal column address counter to increment in synchronization with the RE clock. If the 00h, 01h, or 50h command is input to the device in the read mode, the internal column address counter will count up even after the RE signal is input prior to address input. At this mode, at input of the RE signal beyond the last column address, the device will start reading (Memory register) even without address input and may output the Busy signal (Sequential Read is started).
Address input I/O0 to I/O7 00h/01h /50h
WE RE
R/B
Figure 33
RE Input Before Address
In this way, once the device enters the read mode, unintentional reading may be started after the RE signal is input prior to addressing; therefore, the RE signal should be input after address input.
34
MBM30LV0064
(12) Invalid block (bad block) The device contains unusable blocks. Therefore, the following issues must be recognized:
Some MBM30LV0064 products have invalid blocks (bad blocks) at shipping. After mounting the device in the system, test whether there are no bad blocks. If there are any bad blocks, they should not be accessed. The bad blocks are connected to sense-amp of the bit lines via the selector transistors. Good blocks will not be affected unless the bad blocks are accessed. The effective number of good blocks specified by Fujitsu is shown below. Min. Bad Block Valid (Good) Block Number 1014 Typ. 1020 Max. 1024 Unit Block
Bad Block
Figure 36. Shows the Bad Block Test Flow
Figure 34
Bad Block
(13) Failure Phenomena for Program and Erase Operations Repeated rewriting might cause an error at programming and erasing. Possible error modes, and detection methods and remedies are listed in the following table. System-based remedies will provide a highly reliable system. Failure Mode Block Page Single Bit* * : (1) or (2) * ECC Error Correcting code Hamming Code etc. Example : 1 bit correction & 2 bit detection. * Block Replacement :
Program error occurs Buffer Memory Block A If an error occurs in block A, reprogramming from the external buffer to block B. Block A should not be accessed after an error occurs.
Detection and Countermeasure Sequence Status Read after Erase Block Replacement Status Read after Prog. Block Replacement (1) Block Verify after Prog. Retry (2) ECC
Erase Failure Program Failure Program Failure `1' `0'
Block B
Figure 35
Reprogramming to Good Block
Erase If an error occurs at erasing, like programming, remedies should be executed on a system basis to prevent access to blocks causing the error. 35
MBM30LV0064
(14) ALE Input Condition during Address Input The ALE input must remain high once asserted until the last address byte has been written to the device.
Read Operation CLE CE WE ALE Inhibit "L" Input I/O0 to I/O7 00h, 01h or 50h Address Input
Keep "H"
Program Operation CLE CE WE ALE Inhibit "L" Input I/O0 to I/O7 80h Address Input
Keep "H"
Erase Operation CLE CE WE Keep "H" ALE Inhibit "L" Input I/O0 to I/O7 60h Address Input D0h
36
MBM30LV0064
(15) Inhibit RE Toggling during Busy State The RE input cannot be allowed to toggle during the period that a read data transfer operation is in process (busy state). If the RE input toggles during that period, the internal column address will increment.
CE
CLE ALE WE RE R/B Starting Address Y I/O0 to I/O7 Start from column address Y + X
Toggling X times (Inhibiting)
(16) Restriction on Toggling the WE The WE input cannot be allowed to toggle past the end of page (byte 511 with SE high or byte 527 with SE low) during an input data operation. If the WE input toggles past the end of page, the internal address counter will wrap around to the begging of the page and overwrite the information previously there.
CLE
CE WE ALE Inhibit toggling
RE I/O0 to I/O7 R/B *: DIN for address 511 with SE = "H" or 527 with SE = "L" : VIH or VIL : Invalid Data DIN *
Output Status
80h
DIN
10h
70h
(17) Reading Past Last Device Page When the last byte in the last page of the device is read, the internal address counter will wrap around to the fist page in the device. 37
MBM30LV0064
(18) CE don't care timing for read and program operation CE can be don't-care ("H" or "L") state during read and program operation as follows.

CE
WE RE I/O0 to I/O7 R/B (55 ns Max.) tCEA CE tREA RE I/O0 to I/O7 CE DOUT WE tWP tCS tCH
Command A0 to A7 A9 to A16 A17 to A22
DOUT N
DOUT N+1
DOUT N+2
D DOUT

CE WE I/O0 to I/O7
80h
A0 to A7
A9 to A16
A17 to A22
DIN
0
DIN
1
DIN
2
DIN
*
10h
: VIH or VIL
Note: In the read operation, the CE signal must stay "Low" after the third address input and during Busy state. If the CE signal goes High during this period, the read operation will be terminated and then the standby mode will be entered.
38
MBM30LV0064
s BAD BLOCK TEST FLOW
Test Start
Block No. = 0
Page 1 & 2 Blank Check ]All FFh?^ Yes Block No. = Block No. + 1 Yes B No. > 511 = No Test End
No
Set as a bad block
Figure 36
Bad Block Test Flow
39
MBM30LV0064
s ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM30LV0064 -PFTN
PACKAGE TYPE PFTN = 44-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR = 44-Pin Thin Small Outline Package (TSOP) Reverse Pinout
DEVICE NUMBER/DESCRIPTION MBM30LV0064 64 Mega-bit (8M x 8-Bit) CMOS Flash Memory 2.7 V to 3.6 V Read, Write, and Erase
Valid Combinations Valid Combinations MBM30LV0064 -PFTN -PFTR Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.
40
MBM30LV0064
s PACKAGE DIMENSIONS
44-pin plastic TSOP (II) (FPT-44P-M07)
*: Resin protrusion. (Each side: 0.15(.006) Max)
44
35
32
23
Details of "A" part
0.15(.006)
0.25(.010) INDEX "A" 0.15(.006)MAX 0.40(.016)MAX
LEAD No.
1
10
13
22
* 18.410.10
(.725.004) 0.300.10 (.012.004) 0.13(.005)
M
1.10 -0.05 .043 -.002 (Mounting height)
+0.10
+.004
11.760.20 (.463.008) 10.160.10 (.400.004)
0.150.05 (.006.002)
0.80(.0315)TYP
0.10(.004) 16.80(.661)REF
0(0)MIN (STAND OFF)
0.500.10 (.020.004)
10.760.20 (.424.008)
C
2000 FUJITSU LIMITED F44016S-1C-3
Dimensions in mm (inches)
(Continued)
41
MBM30LV0064
(Continued)
44-pin plastic TSOP (II) (FPT-44P-M08)
*: Resin protrusion. (Each side: 0.15(.006) Max)
44
35
32
23
Details of "A" part
0.15(.006)
0.25(.010) INDEX "A" 0.15(.006)MAX 0.40(.016)MAX
LEAD No.
1
10
13
22
16.80(.661)REF 0.80(.0315)TYP 0.10(.004) 0(0)MIN (STAND OFF) 0.500.10 (.020.004) 10.760.20 (.424.008)
0.300.10 (.012.004)
0.13(.005)
M
1.10 -0.05 .043 -.002 (Mounting height)
+0.10
+.004
* 18.410.10
(.725.004)
10.160.10 (.400.004) 11.760.20 (.463.008)
0.150.05 (.006.002)
C
2000 FUJITSU LIMITED F44017S-1C-3
Dimensions in mm (inches)
42
MBM30LV0064
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0012 (c) FUJITSU LIMITED Printed in Japan

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